/*
 * wire delays test
 */

module cucu;
 input i;
 output o;
 wire #(1,2,3) w;
 wire ww;
 reg r;
 assign #(1, 2, 3) w = r, ww = r;
 
 
initial begin
 r = 'bz;
#5;
 r = 0;
 #5;
 r = 1;
 #5;
 r = 'bz;
 #5;
end
endmodule
